`timescale 1ns/1ps
module booth_multiplier(
    input  signed [31:0] mul_src1,  // 被乘数
    input  signed [31:0] mul_src2,  // 乘数
    output signed [63:0] mul_result // 乘法结果
);

    reg signed [63:0] product;      // 乘积寄存器
    reg signed [31:0] multiplicand; // 被乘数寄存器
    reg signed [31:0] multiplier;   // 乘数寄存器
    reg [5:0] count;                // 计数器
    reg prev_bit;                   // 上一位

    always @(*) begin
        multiplicand = mul_src1;
        multiplier = mul_src2;
        product = 0;
        count = 0;
        prev_bit = 0;

        while (count < 32) begin
            // 检查当前位和上一位
            case ({multiplier[0], prev_bit})
                2'b01: product = product + (multiplicand << count); // 加被乘数
                2'b10: product = product - (multiplicand << count); // 减被乘数
                default: ; // 不做操作
            endcase

            // 更新上一位
            prev_bit = multiplier[0];

            // 右移乘数
            multiplier = multiplier >> 1;
            count = count + 1;
        end
    end

    assign mul_result = product;

endmodule